1. Field of the Invention
This invention relates generally to digital computers, and more particularly to the control of memory access operations of a pipelined processor. The invention specifically relates to the use of a "write queue" for delaying the reading of memory locations into which data will be written by write operations waiting in the write queue.
2. Background of the Invention
Reads and writes to memory must be done in an order specified by a computer program when the reads and writes are to the same memory address. Otherwise, a read to a different address from preceding writes may bypass those writes in order to improve the performance of the computer.
The use of a "write queue" for delaying the reading of memory locations that have prior write operations is disclosed in Fite et al. U.S. Pat. No. 5,125,083, issued Jun. 23, 1992, and incorporated herein by reference. A "write queue" receives the write addresses of memory destination operands from an instruction decoding unit, stores the write addresses, and delivers the stored addresses to memory in response to receiving the corresponding write data from an execution unit. When the instruction decoding unit decodes a memory source operand, its read address is compared to the write addresses stored in the write queue, and the instruction decoding unit is stalled whenever at least one of the write addresses in the write queue matches the read address.
Although U.S. Pat. No. 5,125,083 discloses the general operation of a "write queue", continuing advances in pipelined processor design make it practical to process memory access requests in parallel with the decoding and execution of instructions so that requests are queued, prioritized, and stalled at the last possible moment when prevented by conflicts. Accordingly, it is desired to coordinate the operation of the write queue with the queuing and prioritization of memory requests in such a way as to simplify the control logic for stalling memory read requests at the last possible moment when conflicts arise, and for resuming the processing of the memory requests as soon as the conflict is resolved.